From touch at ISI.EDU  Sun Nov  7 22:02:59 2004
From: touch at ISI.EDU (Joe Touch)
Date: Sun Nov  7 22:03:28 2004
Subject: [optical-networks] info on high-speed encoder (64-to-6) from Fri's
	discussion
Message-ID: <418F0C13.3020507@isi.edu>

Hi, all,

I checked into a few issues on the 64-to-6 encoder from the discussion 
on Friday.

Assumptions:

     Input:     optical pulse, width of 40ps
         in one of 64 40ps slots (one per chip)

     Output:    6 bit encoding of the pulse position

Discussion:

First, we need to assume that the input is slightly pre-processed; we 
can't input 40ps signals into electronics. We also can't likely decide 
which 40ps slot a pulse arrives in.

So the first step is assumed to be optical, where we assume there is a 
way (?) to go from the above input to:
     electrical pulse @ 2.4ns (64 40ps slots, i.e., a code word)
     pulse already decoded from offset to separate input wires

At that point:

     Input:    electrical pulse, width of 2.4ns
         on one of 64 input lines

     Output:    6 bit encoding of input line address

This turns out to be easy, unlikely to be COTS-available already, but a 
'matter of implementation'. CMOS circuits at 2.5 GHz turn out to be 
fairly easy in 0.18 micron technology, which is not exotic. Things get 
hard up around 5 GHz. FYI, this still requires some fairly complicated 
circuit board design (to get electrical signals in at that speed), but 
nothing impossible.

MOSIS does have a free service for this technology for research 
projects, and I believe we'd qualify.

However, it's not necessarily interesting to actually do. It assumes 
we've solved the "optical pulse offset to electrical wire input" 
problem, which seems (to me) to require integrated optics. I'd say we 
have enough to prove that this problem can be solved, but that it's 
large enough that it's not useful to do in this project.

Joe
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